Advanced Computer Architecture, Comparative Architectures Past Paper

Textbook: Hennessy, J. and Patterson, D. (2012). Computer architecture: a quantitative approach. Elsevier (3rd/4th/5th ed.)

Trends

Early computers exploit Bit-Level Parallelism.

• y2020p9q4 (a)

Scalar pipeline

Two-level branch predictor

• y2019p8q3 (a)

Branch Target Buffer (BTB)

• y2023p8q1 (a,b)
• y2020p8q3 (b,c)

Multiple / Diversified pipelines

Improvements

• y2018p27q5 (a)
  • I/D caches

Superscalar pipeline

Exploits Instruction-Level Parallelism.

Instruction Fetch, DEcode, [Rename], [Dispatch: static/dynamic scheduling], [Issue], EXecute, Memory, Write Back.
In-order dispatch: stall for data hazards; In-order issue: stall for structural hazards.

In-order vs out-of-order dispatch & execution

• y2023p8q1 (c,d)
• y2020p8q3 (a)
  • pipeline diagrams
• y2018p27q5 (b)
  • power consumption

Rename: arch (or logical) register $\rightarrow$ physical of the last destination targeted.

• to remove false (or name) dependencies (anti-:WaR, output:WaW).
  • Register Map Table (RMT), Free Physical Register List (FPRL);
  • VLIW: Rotating Register File (RRF).
• y2024p8q1 (a)
• y2019p8q3 (b)

Hardware-based speculation

Load bypassing

• y2018p27q5 (c)
• y2021p9q4 (a.b)
  • memory-carried dependencies

Store queue / buffer

• y2024p8q1 (b)

ReOrder Buffer (ROB) [precise exceptions]

• y2024p8q1 (c)
  • ROB vs Unified Physical RF

Software ILP (VLIW)

Exploits Instruction-Level Parallelism via static scheduling (out-of-order).

Memory reference speculation

• y2018p27q5 (d)

Variable-length bundles of independent instructions

• y2021p8q3 (b)

Multi-threaded processors

Exploits Thread-Level Parallelism.

Coarse-grained MT

• y2024p9q1 (a)

Fine-grained MT

• y2024p9q1 (b)
• y2021p8q3 (a)
  • VLIW vs fine-grained multi-threaded
  • round-robin thread schedule, functional units

SMT

• y2024p9q1 (c)
• y2020p9q4 (b,c)
  • threads characteristics
  • SMT vs Multi-core
• y2018p8q2 (d)
  • (store) multi-copy atomic

Memory hierarchy

• y2022p9q1 (b)

cache

• y2022p8q1 (b)
  • non-inclusive
• y2018p8q2 (c)
  • merging or coalescing write-buffer

Vector processors / SIMD

Exploits Data-Level Parallelism.

• y2021p8q3 (a.iv)
  • VLIW vs SIMD
• y2022p9q1 (a)

Multi-core processors

Exploits Chip Multiprocessing.

Cache coherence: snoopy protocol

• y2022p8q1 (a)
  • Ring interconnect
• y2019p9q4 (e)
  • MESI

Cache coherence: directory protocol

• y2022p8q1 (c,d)
  • hierarchy of on-chip caches

Memory consistency: SC vs TSO, store atomicity

• y2018p8q2 (a-d)
  • SMT, (store) multi-copy atomic

On-chip interconnection network

• y2019p9q4 (a)
  • virtual channels

Specialised processors

Exploits Accelerator-Level Parallelism.

Domain-Specific Accelerators (DSA)

• y2023p9q1
• y2022p8q1 (e)
• y2021p9q4 (c)
  • Multicore; DSA(s)